Circuit design method and circuit design apparatus

ABSTRACT

Route nets having at least one current path through which a current flows are extracted from among a plurality of route nets each representing a line that interconnects elements of an electronic circuit in electrical connecting relationship from information on an electronic schematic. The extracted route nets is separated into a first subnet of lines where currents flow and a second subnet of lines where no currents flow. A route is determined for each of the first and second subnets. Points on the routes for the first and second subnets are interconnected by another route.

BACKGROUND OF THE INVENTION

The present invention relates to techniques for designing semiconductorintegrated circuits and more particularly to techniques used effectivelyfor designing routes in the semiconductor integrated circuits.Particularly, the present invention relates to techniques usedeffectively for designing the wiring for interconnection of componentsthat compose an analog circuit built in a semiconductor integratedcircuit.

A maze method or a channel allocating method is known as a process fordetermining routes in a semiconductor integrated circuit in theirdesign. In the maze method, a label “1” is attached to a cell next to aparticular cell (starting point) of a matrix corresponding to a linecell; a label “2” to a cell next to the label “1”, and so on. In thisway, labels are sequentially attached. If a target cell is reached, thesuccessive labels “1”, “2”, “3” . . . are traced from the beginning tothereby search for the route.

In the channel allocating method, a route is determined for each ofwiring areas (channels) provided between cells. This allocating methodis used widely in interconnecting of logic gates of a digital circuit.An algorithm for determining a route in the maze method/channelallocating method is disclosed, for example, in S. MUROGA, “VLSI SYSTEMDESIGN”, John Wiley & Sons, Inc., 1982, pp. 348-351.

The conventional route determining method is considerably effective forinterconnections of logical gates in a digital circuit. To this end,various automatic routing tools (programs) have been provided. Foranalog circuits, the circuit, characteristics, for example, of anamplifier circuit required by its manufactured article are, however,different from those required by another article. Thus, the circuitcompositions vary little by little and the routes must be determined atthe respective element levels.

There are a few kinds of such automatic routing tools for analogcircuits, but the analog circuits are required to exhibit desiredcharacteristics and sufficient accuracy unlike the digital circuitswhere timings of signals are dominating. Therefore, the conventionalautomatic routing tools for the analog circuits have not sufficientlyattained a reduction in the number of designs, for example, the usermust specify the priority order of determining the route and an outlineof the route.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a routedesign method reduced in man-hours of design suitable for an automaticwiring design of an analog circuit.

An object of the present invention is to provide a circuit designsupporting tool (program) that reduces the man-hours of design in thedesign of routes in an analog circuit to thereby enable the user todesign the routes efficiently.

Another object of the present invention is to provide a circuit designsupporting apparatus that reduces the man-hours of design in the designof routes in the analog circuit to thereby enable the user to design theroutes efficiently.

Still another object of the present invention is to provide a circuitdesign apparatus capable of reducing the number of designs in the routedesign of an analog circuit and enabling the user to perform the routedesign.

These and other objects and novel features of the present invention willbe obvious from the description of this specification and theaccompanying drawings.

In order to achieve the above objects, according to one aspect of thepresent invention, there is provided a method or program of designing,or supporting the design of, a circuit comprising the steps of:

inputting information on a schematic representing a circuit comprising aplurality of elements and a plurality of lines that interconnectsrespective terminals of the plurality of elements, and a value of apower supply voltage fed through a particular one of the plurality oflines that interconnect the respective terminals of the plurality ofelements;

detecting a path through which an electrical current flows in thecircuit based on the inputted information on the schematic;

extracting routing nets each of which comprises a route through which anelectrical current flows from among routing nets each comprising atleast one line that interconnects terminals of ones of the plurality ofelements in electrical connecting relationship from the inputtedinformation on the schematic;

separating each of the extracted routing nets into a first subnetcomprising a line through which an electrical current flows and a secondsubnet through which no electrical current flows; and

generating a constraint condition by which a route is determined foreach of the first and second subnets.

According to the above method or program, each of the extracted routingnets is separated into the first subnet comprising a line through whichan electrical current flows and the second subnet through which noelectrical current flows, and a route is determined for each of thefirst and second subnets. Thus, the route is determined efficiently inthe automatic routing design and the time required for the route designis reduced.

When the plurality of elements of the circuit comprise a bipolartransistor, the path detecting step or function is performed by assumingthat no electrical current flows into the bipolar transistor through itsbase terminal. Thus, since the number of paths in the designed circuitthrough which the electrical currents flow is limited, the routedetermining algorithm is simplified to thereby determine the routeefficiently. Even when such assumption is made, the determined routedoes not greatly affect the characteristics of the circuit because thebase current is by far small compared to the collector current.

Preferably, when the first and second subnets are interconnected, theconstraint condition generating step comprises generating a constraintcondition that prevents a current, which would otherwise flow due tointerconnection of the first and second subnets, from flowing throughthe second subnet. Thus, the automatic routing process performs a routedesign that prevents an electrical current from flowing through anundesirable path.

The schematic information inputting step or schematic information inputsupporting function may comprise inputting data that specifies a pair ofelements among the plurality of elements of the circuit. When a requiredaccuracy of the circuit is high, the constraint condition generatingstep or function may comprise interconnecting the route for the firstsubnet to a midpoint of the route for the second subnet thatinterconnects terminals of the pair of elements corresponding to eachother. Thus, the automatic route design is made which prevents thevoltages on the pair of elements from becoming imbalanced.

The schematic data inputting step may comprise inputting data specifyinga pair of elements among the plurality of elements of the circuit anddata specifying the accuracy of the pair of elements. When accuracy ofthe pair of elements is inputted or when the inputted accuracy is higherthan a predetermined value, the constraint condition generating step maycomprise connecting a midpoint of a line of the first subnet thatinterconnects the terminals of the pair of elements corresponding toeach other with a line of another subnet. Thus, a design of a differentrequired accuracy is possible for each pair of elements to therebyprovide a circuit of increased accuracy.

The midpoint of the route for the subnet may be at equal distances froma contact point where the route is interconnected to the first terminaland another contact point where the route is interconnected to thesecond terminal. Thus, the automatic routing is made which prevents thevoltages on a more accurate pair of elements from becoming imbalanced.

The use of the above-mentioned method or program in the route design forthe analog circuit serves to decrease the man-hours of design and to doefficient designing work.

According to another aspect of the present invention, there is alsoprovided a circuit designing apparatus comprising:

a storage device in which the circuit design supporting program of theinvention is stored;

a computer for reading the program from said storage device and forexecuting the program;

an input device for inputting required data to said computer; and

a display device for displaying a schematic whose data is inputted bysaid input device.

According to such circuit designing apparatus, especially, efficientanalog circuit design is achieved which is accomplished in a minimum ofman-hours of design.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flowchart of a process for designing a route of an analogcircuit according to the present invention.

FIG. 2 illustrates an input picture of a schematic to be used in thedesign method according to the present invention.

FIG. 3 illustrates a pair input form displayed when a pair of elementsis specified in an input picture of a schematic to be used in the designmethod according to the present invention.

FIG. 4 is a schematic of an analog circuit as one example of a circuitto be designed in the design method according to the present invention.

FIGS. 5A-5D illustrate one example of subnet division to be performed inthe design method according to the present invention.

FIG. 6 illustrates another example of subnet division to be performed inthe design method according to the present invention.

FIGS. 7A-7D each illustrate a layout of a pattern of a route to bedisposed by automatic routing design based on a schematic.

FIG. 8 is a sequence of layouts indicative of a process for producing aroute pattern to be disposed in an automatic routing design based onsubnet division and generation of a routing constraint to be performedin the inventive design method.

FIGS. 9A and 9B are a layout of transistors Q11 and Q12, a resistor 5and capacitance C1 and lines extending among them in FIG. 4, and across-sectional view of the capacitor structure, respectively.

FIGS. 10A and 10B are a schematic of a MOS circuit as one example of acircuit designed in the inventive design method, and a layout of severalelements of the circuit.

FIG. 11 is a block diagram of a system for executing the inventive routedesign method effectively.

DESCRIPTION OF THE EMBODIMENTS

Embodiments of the present invention will be described with respect tothe accompanying drawings.

FIG. 1 is a flowchart indicative of a route designing method for ananalog circuit according to the present invention. In this method, auser or a designer views a picture displayed on a display device of acomputer while inputting data on a schematic, selecting a pair ofelements, and specifying a power supply line and voltage relationshipdata (step S1). The pair of elements will be described in greater detaillater. When the schematic data is inputted, a parts list PTL isdisplayed in a portion (on the right side) of a picture, for example ofFIG. 2, using a work list OPL displayed on the left side of the picture.A desired part or element is selected with a mouse in the list anddisposed in a work area at the center of the picture. The user instructsthe computer to depict wiring for interconnection of the elements.

More specifically, first, a parts-list display button PLB is firstclicked in the work list OPL to display a window of the parts list PTLthat indicates arrangement of elements such as bipolar transistorsBTnpn, BTpnp, a MOS transistor MTr, a resistor R, a capacitor C, a diodeD, etc., that compose the analog circuit. A desired element is thenselected in the parts list PTL by manipulating the mouse to cause itspointer to point to a button with a symbol representing the desiredelement to be used and by clicking the button. A button DRP thatindicates arrangement (drop) is then clicked in the work list displayedon the left side of the picture to thereby display the symbol of theelement on the work area of the picture. The pointer is then caused topoint to the symbol, and the symbol is then dragged and dropped at anyparticular position.

A button LDR indicative of interconnection line drawing is then clickedin the work list OPL displayed on the left side of the picture tothereby specify an interconnection line drawing mode. A line thatinterconnects a terminal of any element displayed in the work area and aterminal of another desired element is drawn by manipulating the mouseto move its pointer on the picture. If a straight or zigzag line is tobe depicted at this time, such line is adapted to be drawn automaticallyby specifying its starting and end points or a turning in the line. Byrepeating such work, the schematic of FIG. 2 is inputted.

Tools (programs) that support the above work have been supplied by aplurality of EDA (Engineering Design Automation) vendors. For example,one of the tools is “Composer” manufactured by CADENCE. A wiring netproduced by one of the schematic input support tools which are providedby the EDA vendors is available for the present invention.

In addition to the above functions, the schematic input support toolused in the present invention may further have the functions ofspecifying, recognizing and displaying any two elements as a pair ofelements in the schematic displayed in the work area. To realize thesefunctions, a button PAIR that specifies a pair of elements may beprovided in the work list OPL displayed on the left side of the picture.

The “pair of elements” in the specification and attached claims pointsto a pair of elements matching in relative accuracy because the relativeaccuracy of the pair of elements affects the circuit characteristics, asin the case of a pair of differential input transistors in adifferential amplifier. More specifically, in the circuit of FIG. 2, thepair of elements are a pair of transistors Q1 and Q2; Q9 and Q10; andQ11 and Q12 with the base electrodes of each of the pairs of transistorsbeing interconnected to each other to compose a current mirror circuit:a pair of input differential transistors Q3 and Q4 whose emitterelectrodes are interconnected to each other to compose a differentialcircuit: a pair of transistors Q5 and Q6 whose base electrodes areinterconnected to each other to provide a level shift function: and apair of transistors Q7 and Q8 whose base electrodes are interconnectedto each other to provide a constant current source.

In order to input a pair of elements data, the user first clicks thepair specifying button PAIR with the mouse. In response, as shown inFIG. 3, a pair input form PIF is displayed on the picture in the form ofa window. The user then clicks one of the elements to be paired on thework area (schematic) of the picture, using a pointer of the mouse, toselect it as a reference element. The user then clicks a “Base-” buttonin the pair input form PIF. In response, the name of the element (anidentification symbol given beforehand when the circuit data wasinputted) selected by the clicking is displayed in a reference-elemententry column indicated as “Base”.

The user then clicks another element to be paired with the referenceelement, using the mouse pointer, on the work area (schematic) in thepicture and further clicks the “Paired-[Enter]” button in the pair inputform PI. In response, the name of the clicked element is displayed inthe pair of elements column indicated as “Paired”, and selectable pairaccuracies are indicated in an “Accuracy” column. The user selects adesired one from among the pair accuracies. The “pair accuracy”represents in percentage a tolerance of deviation of a terminal voltageof each of a pair of elements.

The user then clicks a “Set” button in the pair input form PIF. Inresponse, the input support tool recognizes that the specified twoelements are paired. Information indicating that the specified twoelements are paired is then displayed in a field “Pair List” of the pairinput form PIF and a broken-line ellipse P that surrounds the twoelements is shown, for example, by P in FIG. 3 to clearly indicate thatthe two elements are paired in the schematic of the picture. The userthen clicks a “File-” button in the pair input form PIF to thereby storethe information on the paired elements in a predetermined file in astorage device of the system and to terminate the paired-elementsspecifying process.

In addition to the above functions, the schematic input support toolused in the present invention has the function of recognizing theflowing direction of the current when the power supply line is specifiedin the schematic displayed in the work area and voltage relationshipdata is inputted. In order to realize this function, a button VPS thatinputs voltage relationship data is provided in the work list OPLdisplayed on the left side of the picture. In order to cause the supporttool to recognize the flowing direction of the current, a line thatcomposes the power supply line is first clicked by the mouse in theschematic and the button VSP is then clicked. In response, a windowappears on the picture, so that when a value of the power supply andcalculation expressions are inputted, the support tool recognizes thevoltage relationship data, and detects the flowing route and directionof the current in the drawn schematic (step S2). Although the detectedflowing route and direction of the current are not displayed in thesystem of this embodiment, they can be displayed by arrows and referencenumerals I1-I5 in FIGS. 2 and 3.

In order to realize the above functions easily, it should be beforehanddefined, for example, that a bipolar transistor allows a current to flowbetween its collector and emitter; that a MOS transistor allows acurrent to flow between its source and drain but does not allow acurrent to flow between its gate and each of its source and drain; thata resistor allows a current to flow from its higher potential to a lowerone; that a capacitor does not allow a (direct) current to flowtherethrough; and that a diode allows a current to flow therethroughonly in the forward direction. In addition, the support tool should havethe function of tracing the power supply line and the lines connected tothe power supply line, and sequentially searching for paths throughwhich currents flow from the higher power supply voltage to the lowerone.

The feature of the present invention lies in the fact that no current,i.e., a 0 base current, flows between the base and the collector andbetween the base and the emitter of the bipolar transistor being givenas a definition or condition (hereinafter referred to as a “fictitiousdefinition”) in the support program. This causes the number of pathsthrough which currents flow to be limited in the schematic to bedesigned. Thus, an algorithm that determines routes in an analog circuitto be described below is simplified to thereby determine the targetroutes efficiently. Although the fictitious definition is given, thedetermined routes do not greatly influence the characteristics of thecircuit. This is because even though routes are determined bydisregarding the base current the wiring does not greatly influence thecircuit characteristics since the base current is smaller than thecollector current by two or three orders of magnitude. This is alsobecause when high accuracy is required, it can be brought about bygiving a constraint of midpoint interconnection, as will be described instep S5 later.

In step S3, a net having two or more terminals through which no currentsflow and having the current path detected in step S2 is extracted as aone to which a constraint should be added in automatic routing. This isalso performed automatically by the support tool. As shown by a thickline in FIG. 4, the extracted net is highlighted so as to bedistinguished from other nets.

The “net” referred to here is a term used generally in the route design,and points to one or more lines (branch-like wiring) that interconnectterminals of elements placed in electrical connecting relationship, thatis, a series of lines placed at the same voltage level when the elementshave terminals interconnected to each other and no currents flow throughthe terminals. More specifically, for example in FIG. 2, one netcomprises a combination of a line 11 that interconnects the baseterminals of the transistors Q1 and Q2, a line 12 that interconnects thebase and collector electrodes of the transistor Q1, a line 13 thatinterconnects the collector electrodes of the transistors Q3 and Q4, anda line 14 that interconnects the line 13 and the collector electrode ofthe transistor Q1. If this net is called a net A, the net can beexpressed as net A=(Q1-B, Q2-B, Q1-E, Q3-C, Q4-C). A line 15 itself thatinterconnects the emitter electrodes of the transistors Q4 and Q5themselves composes a net. If this net is called a net B, the net can beexpressed as net B=(Q4-E, Q5-E).

When the target net is extracted in step S3, the extracted net isseparated automatically by the support tool into a subnet of lines wherecorresponding currents flow and a subnet of lines where no correspondingcurrents flow. Although there has been in the past the concept that anet is separated into a plurality of subnets in the automatic routingdesign in the past, the concept that a net is separated into a subnetwhere currents flow and a subnet where no currents flow is created forthe first time by the present invention as far as the inventors know. Inthe present invention, the net where the base current flows in thebipolar transistor is classified as the “subnet where no currents flow”in the routing design process as far as the circuit is concerned. Thissubnet separation can be expressed, for example, as net A=((Q1-B, Q2-B),(Q1-E, Q3-C, Q4-C)).

One example of the subnet separation is shown in FIGS. 5A-5D, whichshows that the base electrodes of transistors Q23 and Q24 are connectedto the junction point of series connected transistor Q21 and Q22 whereinthe transistors Q23 and Q24 are paired so that these transistors havethe same base-emitter voltage Vbe.

Note a thick-line net C that interconnects the emitter electrode (Q21-E)of the transistor Q21, the collector electrode (Q22-C) of the transistorQ22, the base electrode (Q23-B) of the transistor Q23, and the baseelectrode (Q24-B) of the transistor 24 in FIG. 5A. The net C can then beexpressed as net C=(Q21-E, Q22-C, Q23-B, Q24-B). As shown in FIG. 5B, acollector current Ic1 flows through the transistor Q21-Q22, 50 that aline (Q21-E, Q22-C) I11 that connects the emitter electrode of thetransistor 21 to the collector electrode of the transistor Q22 isclassified as a “subnet where a current flows”. Although collectorcurrents Ic2 and Ic3 flow through the transistors Q23 and Q24,respectively, no current flows through a line (Q23-B, Q24-B) I12 thatinterconnects the base electrodes of the transistor Q23 and Q24. Thus,the line I12 is classified as a “subnet where no current flows”. Thus,the net C of the FIG. 5A circuit can be separated into two subnets shownby thick lines in FIG. 5C. This subnet separation may be expressed asnet C=((Q21-E, Q22-C), (Q23-B, Q24-B)).

FIG. 6 shows another example of the subnet separation. The circuit ofFIG. 6A shows the transistors Q7 and Q8 of the FIG. 2 circuit havingbase electrodes interconnected to each other, the transistor Q6 thatprovides a base voltage potential of the transistors Q7 and Q8, andresistors R1, R2 and R3 interconnected between the respective emitterelectrodes of the transistors Q6, Q7 and Q8 and ground. In this circuit,the transistors Q7 and Q8 are paired so as to have the same base-emittervoltage Vbe.

Note a thick-line net that interconnects the emitter electrode of thetransistor Q6 and the base electrodes of the transistors Q7 and Q8. Asshown in FIG. 6B, a current I3 flows from the transistor Q6 to theresistor R2. Thus, a line I21 that interconnects the emitter electrodeof the transistor Q6 and the resistor R2 is classified as the “subnetwhere a current flows”. Since no current flows through a line I22 whichinterconnects the base electrodes of the transistors Q7 and Q8 althoughcollector currents I1 and I2 flow through the transistors Q7 and Q8, theline I22 is classified as the “subnet where no current flows”. Thus, aline I21 that interconnects the emitter electrode of the transistor Q6and the resistor R2 is classified as the “subnet where a current flows”.Thus, the net of the FIG. 6(a) circuit is separated into two subnets asshown respectively by thick lines in FIGS. 6B and 6C.

Referring back to FIG. 1, when the target net is separated into thesubnets, in step S5 a routing constraint is generated, which comprises(1) determining routes for the “subnet where no currents flow” and the“subnet where currents flow” by regarding them as separate nets, andinterconnecting the subnets; (2) seeing that no currents flow throughthe “subnet where no currents flow” when the subnets are interconnected;or (3) selecting inter-midpoint interconnection of the subnets when highaccuracy is required for the circuit and any-point interconnection whereno interconnection position is specified when no high accuracy isrequired. The above routing constraint (3) may be inputted by the userat the keyboard. For all pairs of elements, the constraint to selectinter-midpoint connection automatically may be generated. The constraint(2) about the interconnection between the subnets is specifically thatat least a part of a route corresponding to the “subnet where currentsflow” does not overlap with a route corresponding to the “subnet whereno currents flow”. In the example of FIG. 6, the route corresponding tothe “subnet where no currents flow” (FIG. 6B) intersects at one pointwith the route corresponding to the “subnet where currents flow” (FIG.6C).

For example, as shown in FIG. 5D, in the circuits of FIGS. 5A-5D therouting constraint comprises determining a path of the line P1 thatinterconnects the base electrodes of the transistors Q23 and Q24, a pathof the line P2 that interconnects the emitter and collector electrodesof the transistors Q21 and Q22, and a path of the line P3 thatinterconnects the two routes. In addition, the constraint {circle around(2)} is satisfied only by interconnecting any points on the respectivesubnets in the circuit of FIGS. 5A-5D. At this time, when the constraintof the midpoint interconnection {circle around (3)} is generated, aroute is determined which interconnects midpoints LC1 and LC2 of therespective routes, as shown in FIG. 7A.

The midpoint points out a midpoint of a line extending between contactholes in terminals of the two elements, and not a midpoint betweenopposite ends of the line itself. In an example of FIG. 7A, the midpointpoints out a midpoint LC1 of a line extending between contact holes CNT1and CNT2 of the transistors Q21 and Q22, and a midpoint LC2 of a lineextending between contact holes CNT3 and CENT of the transistors Q23 andQ24. Even if the line extends through the contact hole, as shown by EXin FIG. 7A, the position of the contact hole should be eventuallyhandled as the end of the line.

If there is no constraint of the subnet separation (1), a separate lineinterconnects a line I31 that interconnects the collector and baseelectrodes of the transistors Q21 and Q23., and a line I32 thatinterconnects the collector and base electrodes of the transistors Q22and Q24, respectively, are connected by a separate line as shown in FIG.7B in automatic routing in later step S8 (FIG. 1). In this case, since acurrent flows through a line I33 that interconnects the collector andemitter electrodes of the transistors Q21 and Q22, respectively, avoltage drop occurs across the line I33 to thereby cause the basevoltage levels of the transistors Q23 and Q24 to deviate by the voltagedrop, which influences the circuit characteristic. Thus, in this case,the constraint of the subnet separation is effective.

If there is no constraint of the midpoint interconnection {circle around(3)}, it is possible to determine different routes extending between thetransistors Q21 and Q23 and between the transistors Q21 and Q24,respectively, as shown in FIG. 7C. The reason why the routes of FIG. 7Care determined is that it is assumed that no current flows into thebipolar transistor through its base when the current direction isdetected in step S2. Since the line extending between the collectorelectrode of the transistor Q21 and the base electrode of the transistorQ23. differs in length from the line extending between the collectorelectrode of the transistor Q21 and the base electrode of the transistorQ24 in FIG. 7C, there occurs a difference between the base voltagelevels of the transistors Q23 and Q24 when the base currents flow intothe transistors Q23 and Q24. If the transistors Q23 and Q24 are paired,their respective circuit operations are unbalanced to therebydeteriorate the circuit characteristics. Thus, by giving the constraintof the midpoint interconnection {circle around (3)}, such deteriorationin the circuit characteristics is avoided.

Referring back to FIG. 1, when the routing constraint generating processin step S5 ends, an element arranging process in step S6 is performed.In this process, the user views a picture on the display of the computerwhile manipulating the mouse or the keyboard to specify the position ofan element on the chip. The input picture about the element arrangementhas a composition similar to that of the schematic input picture in FIG.2. In the former picture or in a predetermined one of two picturesdisplayed simultaneously in a multi-window display system, the userarranges desired elements in a work area of the predetermined picturewhile viewing the schematic picture and using the parts and work lists.

Thus, for example, as shown in FIG. 8A, arrangement of the transistorsQ21, Q22, Q23, Q24, . . . is determined. Such process can be performedefficiently, by using an appropriate one of layout tools (programs) thatsupport such work, available from a plurality of EDA vendors.“Virtuoso-XL” available from CADENCE has a similar function.

After the arrangement of the elements ends, the routing constraintsgenerated in step S5 are checked for any inter-midpoint interconnectionconstraint. If there is this constraint, the respective coordinates ofthe midpoints of the subnet routes are calculated (step S7). When a newrouting constraint is generated by the arrangement of the elements, therouting constraints may be updated so as to include the new constraintadditionally.

After the work, the schematic data and the routing constraints generatedin steps S1-S5 and S7 are transferred to the layout tool to cause thelayout tool to perform automatic wiring in consideration of theconstraints (step S8). In the present invention, when, for example, theroutes in the FIG. 5 circuit are designed in the automatic routing instep S8, the routes in the two subnets are separately determined, asshown in FIGS. 8A and 8B, and then a route that interconnects the twosubnets is added. At this time, inter-midpoint interconnection isperformed, using the coordinates of the midpoints of the subnet routescalculated in step S7, when the constraint (3) is included, and a routelayout of FIG. 8C is determined. Note that reference characters C, B andE in FIG. 8A denote the collector, base and emitter areas, respectively,of the bipolar transistor Q2 as well as the corresponding collector,base and emitter areas, respectively, of each of other transistors Q22,Q23 and Q24 of FIGS. 8B and 8C.

FIG. 9A illustrates the transistors Q11, Q12, resistor RS andcapacitance C1 surrounded by a chain line X in FIG. 4 and a wiringlayout. In FIG. 9A, reference symbol VCL denotes a power supply linethat supplies a power supply voltage Vcc. The resistor R5 is made, forexample, of a diffusion layer formed on a semiconductor substrate or apolysilicon layer formed through an insulating film on a semiconductorsubstrate. Reference numeral 51 denotes an outline of the diffusionlayer or polysilicon layer. For example, as shown in FIG. 9B, thecapacitance C1 involves an insulating film 62 formed between a diffusionlayer 61 which is, in turn, formed on the semiconductor substrate 60 andan electrode 63 as one terminal of the capacitance C1 made of aluminumformed on the insulating film 62. Reference numeral 64 denotes anelectrode as another terminal of the capacitance C1 interconnected tothe diffusion layer 61 and formed so as to surround the electrode 63.

If there is a violation of the constraints and this cannot be avoided,the layout tool used in step S8 determines the routes by disregardingthe constraint and displays on the picture that there was the violationof the constraint to thereby prevent the automatic routing process fromstopping due to the inability to avoid the violation of the constraintsthat would otherwise occur.

In step S9 the user checks a result of the automatic routing for aviolation of the constraints with the aid of the layout tool. If thereis a violation of the constraints, the control returns to step S6 tochange the arrangement of the elements, and to cause the layout tool toagain perform automatic routing. When the violation of the constraintsdisappears, the route design is completed.

In the three constraints {circle around (1)}-{circle around (2)}illustrated when the routing constraints were generated, an layout, forexample, of FIG. 7D can occur in which the route that interconnects thebase electrodes of the transistors Q23 and Q24 is symmetrical withreference to a line that interconnects the base electrodes of thetransistors Q23 and Q24 of FIG. 7A. Since such layout produces noimbalance between the pair of elements, no great problem arises in thecircuit characteristic. In such a case, the condition that a route for atarget subnet should be provided on its side nearer a subnet to beinterconnected to the target subnet is not added as a constraint in thepresent embodiment.

It will be seen in the comparison between FIGS. 7A and 7D that thelayout of FIG. 7A is preferable compared to that of FIG. 7D because theformer is shorter in wiring. Thus, of course, the above condition may beadded as the constraint. As the number of constraints increases,however, a time required for the automatic routing process in step S8increases and the number of violations of the constraints increases.Thus, by reducing the number of constraints as in the embodiment, thetime required for the automatic routing process is reduced.

While the route design method in the circuit where the bipolartransistors are used as active elements has been illustrated, thepresent invention is applicable to a route design for the circuits whereMOS transistors are used as active elements.

FIGS. 10A and 10B show an example of a MOS circuit and a layout ofseveral elements of the MOS circuit, respectively. The circuit of FIG.10A illustrates a general differential amplifier in which MOStransistors M1-M5 compose a differential amplifier stage and in whichMOS transistors M7 and M8 compose an output stage. Reference symbols C2and M6 denote an oscillation preventing capacitor and a MOS transistoracting as a resistor, respectively. In FIG. 10A, M1, M2 and M8 denotesubstantially paired matching MOS transistors. Each of groups M3 and M4,M5 and M7 is paired matching MOS transistors.

FIG. 10B illustrates circuit elements that comprise MOS transistorsM1-M4 surrounded by a chained-line Y in FIG. 10A, and its wiring layout.In FIG. 10B, reference numeral 71 denotes a diffusion layer that formsthe source and drain areas of the MOS transistors M1 and M2; 72 adiffusion layer that forms the source and drain areas of the MOStransistor M3; 73 a diffusion layer that forms the source and drainareas of the MOS transistor M4; 81 the respedtive gate electrodes of theMOS transistors M1 and M2; 82 the gate electrode of the MOS transistorM3; and 83 the gate electrode of the MOS transistor M4. The diffusionlayers and gate electrodes are each made of a polysilicon layer.

Reference numeral 91 denotes a line made, for example, of aluminum thatapplies a power supply voltage Vcc to the source electrodes of the MOStransistors M1 and M2; 92 a line that interconnects the drain electrodesof the MOS transistors M1 and M3; 93 a line that interconnects the drainelectrodes of the MOS transistors M2 and M4; 94 a line thatinterconnects the source electrodes of the MOS transistors M3 and M4;and 95 and 96 lines that interconnect the gate electrodes and inputterminals IN and {overscore (IN)} of the MOS transistors M3 and M4,respectively.

In this embodiment, the line 92 constitutes a net indicated by a thickline in FIG. 10A that interconnects the gates of the MOS transistors M1and M2 and the drain electrode of the MOS transistor M3. The MOS circuitof FIG. 10B has no constraint of the midpoint interconnection {circlearound (3)}. Thus, the line 92 is interconnected at a position deviatingfrom the midpoint of the gate electrodes 81 of the MOS transistors M1and M2. This is because no current flows into the gate electrode of eachof the MOS transistors unlike the base electrodes of the bipolartransistors, and voltages at respective points on the gate electrode 81are small and the required accuracis of the paired matching elements aresatisfied even when they are not subjected to the midpointinterconnection.

FIG. 11 illustrates a system to which the inventive route design methodis applied effectively. In FIG. 11, reference numeral 100 denotes apersonal computer; and 200 an external storage device such as an opticaldisk driver or an additionally writable CD driver. The personal computer100 comprises a computer proper 110, a keyboard 120 and a mouse 122 asinput devices that input data to the computer proper 110, and a display140 that displays, for example, a schematic whose data was input by theinput devices.

In this system, the personal computer 100 is interconnected by a cable300 to the external storage device 200 so that data is transferable byan interface such as ATAPI (AT Attachment Packet Interface) or a SCSI(Small Computer System Interface). The route design support programcreated by the present invention is stored in a medium 400 such as anoptical or compact disc to be inserted into the external storage device200. The personal computer 100 reads and executes the program to therebyperform the automatic routing design.

While in the above the present invention has been illustrated using itsembodiment, the present invention is not limited to the embodiment.Various changes and modifications are possible without departing thespirit and scope of the present invention, of course. For example, inthe above embodiment, when the constraint of the midpointinterconnection is generated depending on the required accuracy of thepaired matching elements in the wiring constraint generating step S5,the midpoint of the subnet where currents flow is illustrated as beinginterconnected to the midpoint of the route of the subnet where nocurrents flow, as shown in FIG. 8C. In this case, at least the subnetwhere no currents flow or the subnet where the paired matching elementsare present is only required to be midpoint-connected. The route may bedetermined so that the midpoint of the subnet where no currents flow isinterconnected to any one of points on the subnet where currents flow.Even in doing so, the paired matching MOS transistors of FIG. 8 aresupplied with the same base voltage to thereby avoid imbalance indynamic characteristic.

While in the above description the application of the present inventionto a designing system for semiconductor integrated circuits in thebackground of the invention has been illustrated, the present inventionis applicable widely to designing electronic circuits, especially analogcircuits, formed on a printed board, using a computer.

What is claimed is:
 1. A method of designing a circuit comprising thesteps of: inputting information on a schematic representing a circuitcomprising a plurality of elements and a plurality of lines thatinterconnects respective terminals of the plurality of elements, and avalue of a power supply voltage fed through a particular one of theplurality of lines that interconnects the respective terminals of theplurality of elements; detecting a path through which an electricalcurrent flows in the circuit based on the inputted information on theschematic; extracting routing nets each of which comprises a routethrough which an electrical current flows from among routing nets eachcomprising at least one line that interconnects terminals of ones of theplurality of elements in electrical connecting relationship from theinputted information on the schematic; separating each of the extractedrouting nets into a first subnet comprising a line through which anelectrical current flows and a second subnet through which no electricalcurrent flows; and creating a constraint condition by which a route isdetermined for each of said first and second subnets.
 2. The methodaccording to claim 1, wherein when the plurality of elements of thecircuit comprise a bipolar transistor, said path detecting step isperformed by assuming that no electrical current flows into the bipolartransistor through its base terminal.
 3. The method according to claim2, wherein when said first and second subnets are interconnected, saidconstraint condition generating step comprises generating a constraintcondition that prevents a current, which would otherwise flow due tointerconnection of the first and second subnets, from flowing throughthe second subnet.
 4. The method according to claim 3, wherein saidconstraint condition is that the routes for said first and secondsubnets are free from overlapping with each other.
 5. The methodaccording to claim 1, wherein said schematic information inputting stepcomprises inputting data that specifies a pair of elements among theplurality of elements of the circuit, and wherein when a requiredaccuracy of the circuit is high, said constraint condition generatingstep comprises interconnecting the route for the first subnet to amidpoint of the route for the second subnet that interconnects terminalsof the pair of elements corresponding to each other.
 6. The methodaccording to claim 1, wherein said schematic data inputting stepcomprises inputting data specifying a pair of elements among theplurality of elements of the circuit and data specifying the accuracy ofthe pair of elements, wherein when accuracy of the pair of elements isinputted or when the inputted accuracy is higher than a predeterminedvalue, said constraint condition generating step comprises connecting amidpoint of a line of said first subnet that interconnects the terminalsof the pair of elements corresponding to each other with a line ofanother subnet.
 7. The method according to claim 5, wherein the midpointof the route for the subnet is at equal distances from a contact pointwhere the route is interconnected to the first terminal and a contactpoint where the route is interconnected to the second terminal.
 8. Themethod according to claim 1, wherein the circuit comprises an analogcircuit that includes a bipolar transistor as an active element.
 9. Aprogram for supporting the design of a circuit comprising the functionsof: inputting information on a schematic representing a circuitcomprising a plurality of elements, and a plurality of lines thatinterconnects respective terminals of the plurality of elements, and avalue of a power supply voltage fed through a particular one of theplurality of lines that interconnects the respective terminals of theplurality of elements; detecting a path through which an electricalcurrent flows in the circuit based on the inputted information on theschematic; extracting routing nets each of which comprises at least oneroute through which an electrical current flows from among routing netseach comprising at least one line that interconnects terminals of onesof the plurality of elements in electrical connecting relationship fromthe inputted information on the schematic; separating the extractedrouting nets into a first subnet comprising a route through which anelectrical current flows and a second subnet comprising a route throughwhich no electrical current flows; and creating a constraint conditionby which a route is determined for each of said first and secondsubnets.
 10. A computer readable recording medium that contains thecircuit design supporting program of claim
 9. 11. A circuit designingapparatus comprising: a storage device in which the circuit designsupporting program of claim 9 is stored; a computer proper for readingthe program from said storage device and for executing the program; aninput device for inputting required data to said computer proper; and adisplay device for displaying a schematic whose data is inputted by saidinput device.
 12. A method of designing an electronic circuit,comprising the steps of: analyzing an inputted and displayed schematicrepresenting an electronic circuit that comprises a plurality ofelements each having a terminal and a plurality of lines that eachinterconnect related ones of the terminals, and a value of a powersupply voltage fed by a particular one of the plurality of lines;producing a plurality of route nets each representing a lineinterconnecting terminals of the ones of the plurality of elements inelectrical connecting relationship based on a result of the analysis ofthe schematic; detecting paths of the electronic circuit whereelectrical currents flow, based on the result of the analysis of theschematic; selecting a plurality of route nets each comprising a paththrough which an electrical current flows and at least four terminalsbased on the produced plurality of route nets and paths, and separatingeach of the selected plurality of route nets into a first subnet oflines through which electrical currents flow and a second subnet oflines through which no electrical currents flow; determining routes forthe first and second subnets by regarding the first and second subnetsas separate nets; and interconnecting points on the routes for saidfirst and second subnets.
 13. The method according to claim 12, whereinthe points on the routes for said first and second subnets areinterconnected by another route.
 14. The method according to claim 12,wherein the route for said first subnet intersects at one point with theroute for said second subnet.
 15. A computer executable program forsupporting the design of an electronic circuit, comprising the steps of:analyzing an inputted and displayed schematic representing an electroniccircuit that comprises a plurality of elements each having a terminaland a plurality of lines that each interconnect related ones of theterminals, and a value of a power supply voltage fed by a particular oneof the plurality of lines; producing a plurality of route nets eachrepresenting a line interconnecting terminals of the ones of theplurality of elements in electrical connecting relationship based on aresult of the analysis of the schematic; detecting paths of theelectronic circuit where electronic currents flow, based on the resultof the analysis of the schematic; selecting a plurality of route netseach comprising a path through which an electrical current flows and atleast four terminals based on the produced plurality of route nets andpaths, and separating each of the selected plurality of route nets intoa first subnet of lines through which electrical currents flow and asecond subnet of lines through which no electrical currents flow;determining routes for the first and second subnets by regarding thefirst and second subnets as separate nets; and interconnecting points onthe routes for said first and second subnets.
 16. A computer readablerecording medium that contains the circuit design supporting program ofclaim 15.